Highlights:Senior technical staff with more than 15 years experience in mixed signal and analog VLSI design with extensive exposure and proven track record from product definition, circuit design to post-silicon validation. Solid background in technical leadership and project management, leading highly technically inclined engineering workforce across multi-cultural and multi-national teams (USA, INDIA, MEXICO, ISRAEL, COSTA RICA, GERMANY).

Skills:Mixed signal, analog, DDR, Mixed signal, Analog, High speed, DDR

Goal:To secure a position with a company in which my technical leadership and knowledge will be used to enhance the growth of the company while making an impact to the lives of mankind.

Certification:• DDR PHY circuit architect with extensive exposure on post-silicon Bench DV, platform silicon debug and BIOS based memory training algorithm • Strong exposure on Multi-Gigabit serial IOs(Intel’s Quick Path Interface, HDMI), GPIOs(UART, SDIO, I2C, I2S, eMMC), clocking (DLL, Phase Interpolators, clock distribution) and regulators(LVR, LDO) • Profound knowledge of High Speed Low power Digital and Analog design techniques on Intel’s state of the art 14nm, 20nm, 32nm and 45nm CMOS process technology • Extensive familiarity in Cadence tools, Spice based simulators, Parasitic extraction, Reliability/Aging, Monte-Carlo analysis and Static Timing Analysis(STA) • In-depth knowledge of analog system definition, system architecture, simulation and circuit design • Comprehensive knowledge of transistor level circuit tuning & concepts with emphasis on circuit functionality & robustness and strong understanding of analog layout techniques for performance • Strong analytical skill and extensive lab hands-on on silicon debug techniques to identify analog IO circuit and logic issues. • Proficient in C, PERL, UNIX and Python programming languages

Honor:• Receipient of the pretigious Intel Achievement Award (IAA) 2011 • Co-authored publication papers on “IO Loopback BIST DFT” and “High Efficiency Termination in DDR & LPDDR” for internal conference and “A 2.4Gbps Transmitter with programmable De-emphasis scheme for DDR3 Memory Interface” for IEEE International Conference on 4th Intelligent and Advanced Systems 2012 (ICIAS2012) • Holds 3 US patents with 1 pending in high speed IO circuit architecture field

Senior Staff Analog Engineer 04/2008 - current
Intel, , Malaysia
DDR Lead and Circuit Architect for Intel's 14nm, 22nm and 32nm microprocessor families
• Responsible for the overall DDR PHY IP development for 14nm & 32nm Intel’s next generation microprocessor families which includes defining technical specifications, project deliverables, scheduling tasks, resource line up and conducting circuit & schematic reviews to complete designs on time while meeting robustness and quality. • Led a design team to deliver both front-end & backend DDR IP collaterals and integration. Sets strategic direction and defining key milestones to achieve aggressive 14nm & 32nm product ramp schedule targets. • DDR PHY layer micro-architect where responsible to define PHY layer circuit architecture, analog circuit specification & features, power down states including high voltage power gate architecture to achieve best-in-class area, power and performance. • Responsible for DDR Bench DV, silicon debug to isolate design bugs or circuit issues and defining BIOS memory training algorithms to optimize electrical margin & power. • Responsible for developing site competency & capability building in setting up a DDR Phy team outside of United States and delivering to Intel CPU tick-tock cadence.--
Staff Analog Engineer 04/2006 - 04/2007
Intel, Hillsboro, OR United States
Delivered high speed serial Intel® QuickPath Interconnect (QPI) transceiver design and DDR3 PHY for 45nm Nehalem microprocessor family.
• Delivered high speed serial Intel® QuickPath Interconnect (QPI) transceiver design which includes 8-10 GT/s current mode 2-tap equalization transmitter design and a continuous linear equalization receiver amplifier with offset cancellation scheme for 45nm Nehalem microprocessor family. • Led a backend design team to deliver DDR3 Command, Address & Clock modules for 45nm Nehalem microprocessor which includes HDL translation to optimized logic gates schematic, formal equivalence verification, floor planning & power delivery, signal track planning, static timing analysis, signal integrity and electrical quality checks. Managed project execution and timely reporting, reviewed & defined action/risk mitigation plans and drive area & power targets.--
Senior Component Design Engineer 01/2003 - 04/2005
Intel, , United States
High speed digital and analog circuit design for Intel's next generation CPU/microprocesseor
• Functional block design engineer working in 2 design styles of structured data-path & register-file for 90nm Prescott and 130nm Northwood-V Pentium-4 microprocessor family. • Responsible to translate blocks’ Hardware Description Language (HDL) to schematics and optimize for latency and silicon real-estate. Performed Formal Equivalence Verification (FEV) and Performance Verification (PV) which includes static timing analysis, clocking, signal-integrity, electrical-rule, guiding layout/mask engineers. • Responsible for completing transistor level analog circuit designs for Front Side Bus (FSB) I/O transceiver and compensation modules for 65nm Cedarmill Pentium 4 microprocessor family. • Handle the tasks of reviewing analog circuit layout, validation test plan and schematic & simulation design reviews.--
Product Quality and Reliability Engineer 03/1999 - 12/2002
Intel, , United States
Led manufacturing cost reduction to driving test time reduction, yield improvement, eliminating cold socketing and burn-in flow by partnering with cross functional teams from Technology Development (TD), design, division product engineering and manufacturing.
• Led manufacturing cost reduction to driving test time reduction, yield improvement, eliminating cold socketing and burn-in flow by partnering with cross functional teams from Technology Development (TD), design, division product engineering and manufacturing. • Led virtual factory product teams from Malaysia, China & Philippines on identifying and resolving manufacturing yield and quality issues and delivering to aggressive schedule targets to allow a successful steep ramp of Intel® 915 Chipset in Centrino® laptop. • Developed test program content and test vector generation for Intel Northbridge chipsets. Lead the definition and validation of Design for Testability (DFT), test vectors and modules for structural tester by partnering with design team. • Liaison to and from design, division, assembly & test teams. Key decision maker for class test program content, white paper proposal and flows, includes working with class on co-optimization of kills points between sort & class.--

University Science Malaysia 07/1995 - 03/1999
Penang, , Malaysia
Degree: Bachelor's Degree
Major:Microelectronic Engineering
B.Eng(Hons) in Electrical & Electronic Engineering First Class Honours

My Resume