Highlights:

Skills:Verilog, System Verilog, VHDL, C/C++ Perl, Bash & TCL (basic expertise) UVM & OVM, SCEMI 2.0, TBX, Veloce, Emulation, Simulation Acceleration

Lead Engineer, Sr. 01/2011 - current
Qualcomm Inc, Bangalore, KA India
Industry: Semiconductor
ACCELERATED SIMULATION ON VELOCE TBX PLATFORM VI BUILD BRINGUP ON VELOCE ICE PLATFORM FPGA SIMULATION & EMULATION OF COMPLEX MOBILE SoCs
ACCELERATED SIMULATION ON VELOCE TBX PLATFORM (Veloce (OS2/OS3), Verilog/SystemVerilog, SystemC, OVM/UVM, SoC Architecture, Transactors Design, LPDDR1/2/3 Phy and AHB/AXI, PCIe, Accelerated GLS (or GLE) on Veloce) •Accomplished Initiatives: 1.Gate-Level Emulation initiative, delivered Veloce builds with GLS netlist/libs, debugged critical build issues and testbench interface issues for successful deployment of an accelerated GLS on Veloce (also termed as Gate Level Emulation) 2.Created and deployed GPIO and TIC transactors in GLS acceleration 3.Mentored team to bring up EMMC for TBX and ICE builds, which enabled the boot team for pre-silicon testing on Veloce •DDR Bring up in Veloce Environment: Successfully delivered TBX/ICE builds with DDR Phy remodelled (translating behavioural code to synthesizable RTL) for Gen1, Gen2.5 and Gen3 LPPDDR for various projects •Transactor Deployments: 1.Successfully deployed PCIe gen-2 VTL transactor, enabled DV team to execute end-to-end PCIe performance tests. Later I coordinated with boot test team to adopt the same to accelerate the boot-testing 2.Successfully enabled TBX Builds with LPASS, SDCC and PCIe/USB transactor models (which generates AXI traffic) 3.My experience in DV and emulation helps me to debug and bring up the builds quickly •Deployed several automations to enable quicker debug in Veloce compile flow •Analysis of the project requirements, planning, execution and mentoring the team VI BUILD BRINGUP ON VELOCE ICE PLATFORM (Veloce (OS2/OS3), JTAG Boundary Scan, Verilog/SystemVerilog, Virtual JTAG, VI testing, UPF and Power Aware Validation) Contributions •Early deployment of full SoC ICE Builds with GCC, DDR and power-up testing enabled. •Deployed DDR in VI builds for first time in Qualcomm, which was later adopted in all VI builds. •Automated/deployed ICE builds with Trace32 interface through Virtual-JTAG, which enabled VI test teams to use Veloce ICE builds even in slow clock scenarios (PLLs with odd clock ratio) •Enabled clock-control & PLL testing in SoC ICE builds for CLK driver validation on Veloce •Brought up full SoC Power-Aware validation on Veloce (UPF 2.0) enabling power testing such as retention, isolation and power collapse scenarios. •Enabled backdoor loading of LPDDR2 by AXF to VDAT conversion (with Logical to Physical address remapping script) in Veloce Codelink (Offline Debug solution) FPGA SIMULATION & EMULATION OF COMPLEX MOBILE SoCs Description--
Asst. Manager - Electronics 08/2009 - 01/2011
Fowler Westrup, Bangalore, KA India
Industry: Machninery
DESIGN & VERIFICATION OF FPGA BASED CONTROLLER ON REAL-TIME IMAGE PROCESSING SYSTEM
Description It was design and verification project of a FPGA based controller sitting as a master controller on a Snapshot board which has an Altera's Stratix FPGA and four TI DSPs. The FPGA controls camera operations, buffers & pre-processes the raw data from four cameras, then routs it to corresponding DSPs and monitors the DSP execution phases (for pattern detection). The FPGA controller fetches final DSP outputs, compares with rejection criteria, and triggers ejectors in real-time to remove unwanted from food product falling freely from top to the bottom. Skills Verilog, SystemVerilog Tools Quartus II, ModelSim Contributions • Coded Camera-flash control, Image Pre-Processor (converted C code to Verilog equivalent) and Ejection control module. • Created SV testbench to simulate & debug the design. • Involved in planning and monitoring of the production followed by thorough quality tests. Period 17 Months (Aug 2009 – Dec 2010)--
Senior Project Engineer 05/2006 - 04/2009
Wipro Technologies, Bangalore, KA India
Industry: Semiconductor
FUNCTIONAL VERIFICATION OF WiMedia MAC IP FUNCTIONAL VERIFICATION OF ANALOG CONVERSION ENGINE FUNCTIONAL VERIFICATION OF FIBER CHANNEL CONTROLLER "Tachyon QE8+" FUNCTIONAL VERIFICATION OF STORAGE AREA NETWORK CONTROLLER
FUNCTIONAL VERIFICATION OF WiMedia MAC IP This was a WiMedia UWB MAC layer design & verification project in C & Verilog based testbench Skills C, Verilog, PLI, Wimedia, TCP/IP Contributions •Coded multiple testbench modules and testcases •Involved in testbench debugging, reviews and documentation FUNCTIONAL VERIFICATION OF ANALOG CONVERSION ENGINE This was a block level verification of a higher-end Analog Conversion Engine (ACE) of SmartFusion FPGA board for an active interface to the analog world The board was designed based on ARM Cortex-M3 which used to communicate with a set of peripherals over an AMBA based Communications Matrix to provide a range of digital and analog functionality on a single platform Skills Verilog, AMBA Contribution •Designed a cycle accurate ADC model with multiple controls, sampling time control & multi-channel support to cover multiple test scenarios •Implemented FIFO based SRAM BFM for ADC verification •Written multiple testcases and debugged several issues •Involved in planning, testbench architecture and code reviews FUNCTIONAL VERIFICATION OF FIBER CHANNEL CONTROLLER "Tachyon QE8+" It was a Specman based verification project for a high performance Fiber Channel Interface Controller. The State-Machine based quad-core 8 gigabit FC controller had interfaces directly to an 8-lane PCI-Express Gen-II link on the backplane of a host bus adapter and on front plane, controller had support for 4 processors per FC link. Skills Specman 'e' Contribution •Involved in test reviews, regression run and debugging •Wrote testcases targeting encryption module and did eVC improvements •Involved in test reviews FUNCTIONAL VERIFICATION OF STORAGE AREA NETWORK CONTROLLER Description It was a C++ & Verilog based verification project for a Storage-Area-Network Controller; a high performance DMA agent, which interfaces a switch fabric to PCI interface at host. The overall architecture of the system utilizes a store forward model, where data to/from the host (or disk) is assembled into local memory before moving to remote memory. The controller had leveraged the concepts of the PIPE Machine architectures and packet-based protocols of the SRIO fabric and PCI Express. Skills C++, OOP, Verilog & PLI Contribution •Written multiple top level testcases based on test-plan and corner case study. •Done verification for in-circuit emulator (ICE) & boundary-scan (JTAG) module •Involved in testcase/testbench code reviews--
Project Engineer 06/2004 - 03/2006
IIT Delhi & INMAS Delhi, Bangalore, KA India
Industry: R&D
DESIGN OF FPGA BASED EEG SIGNAL ANALYSER AND HMI CIRCUIT DESIGN
This project was basically to design a real-time signal processing system to identify a pathological condition of patient by tracking the changes of EEG frequency spectrum. FPGA Design, VHDL Altera Max+Plus II Designed a combinational multiplier for complex computations of the real-time raw EEG data before DSP operations. The work was selected for technical paper presentation at "GSPx" The Embedded Signal Processing Conference, Sept. 2004 (Santa Clara, USA). Automated Fire Suppression System: This system is based on thermal & pressure sensors for continuous temperature monitoring. It is used to ignite the High-Pressure Fire Extinguishers after getting any indication of Fire/Explosion (within 100 ms). I designed this system with microcontroller 8051 based design.(Dec 2005 – March 2006) Design and Development of Technological Interfaces for Spinal Cord Injury Patients: My role in this project was to design a board based Multimode Blow Switch for Spastic Children to operate 4 Power Switches. It’s an Air Pressure (0 - 5 PSI) driven electronic control system to operate main-power devices, such as Tube light, Fan, TV and Call bell. (June 2004 – Feb 2005)--

DDU Gorakhpur University 07/2001 - 07/2003
Gorakhpur, UP, India
Degree: Master's Degree
Major:Electronics
Full time M.Sc. course.

Resume System Verilog, Verification, Emulation, Veloce, Palladium, FPGA Simulation